1. Field of the Invention
The present invention relates to semiconductor devices and method of fabricating the same, and in particular, to a field effect transistor (FET) having a MIS (Metal-Insulator-Semiconductor) structure.
2. Related Art
As the miniaturization of MOS (Metal-Oxide-Semiconductor) field effect transistors has advanced in accordance with the scaling law, the speed of LSIs has been accelerated, and the high integration of LSIs has been performed. According to the scaling law, the device performance has been improved by simultaneously decreasing the dimensions of both the height and the width of each part of MOSFETs, such as thickness of insulating layers, gate length, etc. For highly miniaturized LSIs produced in the 30-nanometer technology, which are expected to appear after the year 2010, the thickness of gate dielectric is required to be sufficiently thin, so that the equivalent SiO2 thickness (also referred to as “EOT (Equivalent Oxide Thickness)” herein) for the gate dielectric is sufficiently less than 1 nm. However, in a conventional gate dielectric of SiO2, as the thickness thereof becomes 2 nm or less, gate leakage current drastically increases due to direct carrier tunneling. Accordingly, it is impossible to keep the gate leakage current low, thereby causing problems, such as increase of power consumption, etc. In order to overcome these problems, it is necessary to use material with dielectric constant higher than that of SiO2 for gate dielectric. This material is usually called to be “high-k gate dielectric”. High-k gate dielectric can suppress gate leakage current with a low EOT being kept, since its physical thickness (actual thickness) is much thicker than that of SiO2.
Recently, rare-earth metal oxides such as La2O3 (Y. H. Wu, M. Y. Yang, A. Chin, W. J. Chen and C. M. Kwei, IEEE Electron Device Lett. 21, 341 (2000)) and Pr2O3 (H. J. Osten, J. P. Liu, P. Ggaworzewski, E. Bugiel and P. Zaumseil, IEDM 2000 Technical Digest, San Francisco, p. 653 (2000)), which show small EOT and low leakage current density, have been attracting much attention as alternative high-k gate dielectric. Epitaxial single crystalline high-k dielectric directly grown on Si, which enables further reduction of EOT, would be the most promising candidate for the gate dielectric in highly-miniaturized LSIs.
However, it is well known that the elimination of an amorphous interfacial layer between a high-k dielectric and the Si substrate is difficult, and there is few reports regarding to the direct growth of the high-k dielectric on Si. The amorphous interfacial layer is a silicon oxide (SiOx) or a silicate with low dielectric constant. Thus, the capacitance between the Si substrate and the gate electrode is decreased, resulting in large EOT values. Mckee et. al reported direct growth of SrTiO3 on Si and electrical characteristics as gate dielectric (R. A. Mckee, F. J. Walker and M. F. Chisholm, Phys. Rev. Lett. 81, 3014 (1998), R. A. Mckee, F. J. Walker and M. F. Chisholm, Science 293, 468 (2001)).
The present inventors have reported that they have succeeded in the direct growth of CeO2, which is one of the rare earth metal oxides, on Si and realized an ultra-thin EOT value as small as 0.38 nm.
With respect to a gate dielectric of MISFETs, it is important to maintain good interfacial properties with Si, in addition to the suppression of gate leakage current. If many interface states exist between the Si substrate and the gate dielectric, they induce serious degradation of the transistor characteristics due to the decrease in the carrier mobility. However, the interfacial properties of rare-earth metal oxides have not been fully studied. In particular, there has been no report on the interfacial properties of single-crystalline metal oxide directly grown on the Si substrate. In order to realize highly-miniaturized LSIs with good device performances, it is essential to form a high quality interface between the high-k gate dielectric and the Si substrate with the EOT value of 1 nm or less.
High-kmaterials, such as ZrO2, HfO2, Zr silicate, Hf silicate, etc. (silicates are SiO2 containing metals such as Zr or Hf), with which it is possible to achieve the EOT values of around 1 nm, are widely studied as a high-k gate dielectric for the highly-miniaturized LSIs for the next generation (after year 2005). These materials are basically amorphous, but it is known to be easily crystallized during high-temperature annealing processes such as impurity activation annealing for source and drain regions. Attempts have been made to suppress the crystallization and to improve thermal stability of these metal oxides and silicates by adding nitrogen thereto (For example, M. Koyama, K. Suguro, M. Yoshiki, Y. Kaminuta, M. Koike, M. Ohse, C. Hongoand A. Nishiyama, IEDM 2001 Technical Digest, Washington (2001)). However, it has been reported that the addition of nitrogen may degrade the interfacial properties of such amorphous materials. Another conventional way of increasing dielectric constants is the addition of nitrogen to SiO2 to obtain SiON. However, in this case as well, the interface properties at the interface between SiON and Si substrate are inevitably degraded due to the addition of nitrogen.
As described above, the high-k gate dielectric with good interfacial properties is necessary to advance miniaturized LSIs with high integration and improved performances.
However, no high-k gate dielectric with low EOT has been achieved sufficiently good interface properties.